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Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product
Parallel Prefix Adder (PPA) Dot operator Semi-Dot operator
2010/2/2
Parallel Prefix addition is a technique for improving
the speed of binary addition. Due to continuing integrating intensity
and the growing needs of portable devices, low-power and highperformance
...
Low power and less area architecture for integer motion estimation
sum of absolute difference high speed DSP
2010/2/2
Full search block matching algorithm is widely
used for hardware implementation of motion estimators in
video compression algorithms. In this paper we are proposing
a new architecture, which consis...
Multi-view Description of Real-Time Systems’Architecture
Real-time systems Software architecture software component dependability
2010/2/2
Real-time embedded systems should benefit from
component-based software engineering to handle complexity and
deal with dependability. In these systems, applications should not
only be logically cor...
Blocking Performance Evaluation of a Proposed Wavelength Cross Connect Architecture
Blocking probability OXC wavelength routed networks (WRON) optical switching.
2010/7/16
In this work, we study the blocking performance of the individual node: optical cross connects (OXC) with (full or limited) wavelength conversion in wavelength routed networks (WRON) based on the theo...
An Adaptive Digital Fuzzy Architecture for Application-Specific Integrated Circuits
Fuzzy logic Digital integrated circuits Control systems and applications
2010/12/7
A generic fuzzy logic system implementation in digital hardware is presented in this paper. The architecture developed is oriented to Application-Specific Integrated Circuits (ASICs), and its function...